Arm Assembly
Arm assembly targets the Arm architecture, ~87%-owned by SoftBank Group (Arm Holdings plc, Nasdaq: ARM, IPO Sept 2023); over 350 billion Arm-based chips have shipped cumulatively as of early 2026 and Arm cores run ~99% of smartphones. Current silicon implements Armv9-A, which mandates AArch64 support at every exception level while 32-bit AArch32 (A32/T32) is only optional at EL0 — a hard split from Armv8-A's dual-state design. The AAPCS64 calling convention passes the first 8 arguments in X0-X7, returns via X0, uses X8 for indirect struct returns, X19-X28 as callee-saved, and X29/X30 as frame pointer/link register. Official toolchain: Arm GNU Toolchain 15.2.Rel1 (released Dec 2025, based on GCC 15.2), targeting arm-none-eabi for bare metal or aarch64-linux-gnu for Linux userspace. Current version/status: Armv9-A architecture (current profile); Arm GNU Toolchain 15.2.Rel1 (Dec 2025, GCC 15.2-based). License: Proprietary ISA specification (licensed to silicon vendors); reference toolchain (GNU Assembler/GCC) is GPL, LLVM's integrated assembler is Apache 2.0 with LLVM exceptions. Maintained by Arm Holdings plc (Nasdaq: ARM), ~87% owned by SoftBank Group as of 2026 (down from ~90.6% at IPO in Sept 2023); architecture spec authored by Arm, GNU toolchain packaged by Arm in partnership with the GNU project.
Write AArch64 assembly when reverse-engineering iOS/Android binaries, bringing up bare-metal firmware on Cortex-M/A silicon, or hand-tuning NEON/SVE kernels where the compiler leaves performance on the table — nothing else gives register-level control on the chip running nearly every phone on Earth. Skip it for general embedded application logic: C plus intrinsics gets 95% of the speedup at a tenth of the debugging pain, so reach for that instead. Arm's own architecture split is the honest weak point — AArch32 and AArch64 are separate, non-interoperable instruction sets, so the skill you build on one doesn't transfer cleanly to the other despite sharing the "ARM assembly" name.