High Level Synthesis

High Level Synthesis (HLS) is a design automation tool that converts high-level programming languages like C, C++, or SystemC into register-transfer level (RTL) hardware descriptions for digital circuits, such as FPGAs or ASICs. It enables software engineers to design hardware by abstracting away low-level hardware details, accelerating the development of complex systems. HLS tools optimize the generated hardware for performance, area, and power based on user constraints.

Also known as: HLS, C-to-gates, High-Level Synthesis, Electronic System Level Synthesis, Behavioral Synthesis

Why learn High Level Synthesis?

Developers should learn HLS when working on hardware-software co-design, embedded systems, or accelerating algorithms in fields like signal processing, machine learning, or telecommunications, as it reduces design time and allows for rapid prototyping. It is particularly useful for FPGA-based projects where traditional RTL coding in VHDL or Verilog would be too time-consuming, enabling faster iteration and verification cycles.

Learning Resources

• docs: Xilinx Vitis HLS Documentation
• docs: Intel High Level Synthesis Compiler User Guide
• course: Coursera: FPGA Design for Embedded Systems
• video: YouTube: Introduction to High-Level Synthesis
• book: Book: High-Level Synthesis: From Algorithm to Digital Circuit