3D Integrated Circuits
3D-IC vertically stacks active dies via through-silicon vias (TSVs) or hybrid bonding, versus 2.5D packaging which places dies side-by-side on a silicon interposer connected by TSVs embedded in the interposer itself, not the dies. TSMC's SoIC hybrid-bonding process is in mass production at roughly 9-micrometer bond pitch as of TSMC's 2026 North America Technology Symposium, with a roadmap to 6 micrometers (N2-to-N2) by 2028 and 4.5 micrometers (A14-to-A14) by 2029; SoIC-P uses bumped stacking for cost-sensitive designs, SoIC-X is bumpless for HPC/AI use. Interposer TSVs typically run 5-20 micron diameter, 80-120 micron deep. TSMC is guiding CoWoS capacity toward roughly 125,000-130,000 wafers/month by end of 2026 and remains the dominant leader in advanced-packaging capacity, though no specific market-share percentage could be verified against the PatSnap source. No single vendor owns the category: Intel (Foveros Direct) and Samsung (X-Cube) compete directly. Current version/status: SoIC hybrid bonding: ~9um bond pitch in mass production (2026 TSMC Tech Symposium), roadmap to 6um (N2-to-N2) by 2028 and 4.5um (A14-to-A14) by 2029. License: N/A -- proprietary fab processes per vendor (TSMC SoIC/CoWoS, Intel Foveros Direct, Samsung X-Cube); JEDEC (JC-63) sets cross-vendor memory-stacking interop standards. Maintained by No single maintainer -- led by TSMC (SoIC/CoWoS), Intel (Fove
Pick 3D-IC TSV/hybrid-bonding stacking when bandwidth-per-watt trumps everything else -- AI accelerators and HPC compute, where TSMC's SoIC-X bumpless bonding buys shorter vertical interconnects than any side-by-side layout can. Don't reach for it in cost-sensitive or high-power-density designs: peer-reviewed cost/thermal modeling puts 2.5D interposer integration as more cost-efficient once power density climbs past roughly 0.4 W/mm^2, because a hot logic die buried under a memory die can't shed heat as directly as 2.5D's side-by-side layout. The honest weakness the field admits itself: known-good-die testing before bonding is still unsolved, so a defect in a buried die can't be reworked and yield loss compounds across the stack. Known weakness: Known-good-die testing before bonding remains unsolved: a defect in a die already buried under another die can't be reworked, so yield loss compounds across the stack, and TSV-stacked logic traps heat that a 2.5D side-by-side layout can vent more directly.